Codigo Vhdl Conversor Binario A Bcd

–ESCALIZACIÓN Y BCD PARa un numero de 4 cifras
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity ConvBinBCD is
port (
Dx_volt : in std_logic_vector (7 downto 0);
num_bcd_volt : out std_logic_vector (19 downto 0)
);
end entity ConvBinBCD;

architecture BH of ConvBinBCD IS
signal s_num_bcd_volt : std_logic_vector (19 downto 0);
signal Mult1 : integer;
signal Dx_int : integer;
signal Mult_out : std_logic_vector(16 downto 0);
constant mult : integer := 352;
begin
Dx_int <= to_integer(unsigned(Dx_volt));
Mult1 <= Dx_int * mult;
Mult_out <= std_logic_vector(to_unsigned(Mult1,17));

BCD : process (mult_out)
variable z: std_logic_vector(36 downto 0);
begin
z:= (others=>’0′);
z(19 downto 3) :=mult_out;
for i in 0 to 13 loop
–Unidades(4 bits)
if z(20 downto 17) > 4 then
z(20 downto 17) := z(20 downto 17) +3;
else z(20 downto 17) := z(20 downto 17);
end if;

–Decenas (4 bits)
if z(24 downto 21) > 4 then
z(24 downto 21) := z(24 downto 21) +3;
else z(24 downto 21) := z(24 downto 21);
end if;

–Centenas (4 bits)
if z(28 downto 25) > 4 then
z(28 downto 25) := z(28 downto 25) +3;
else z(28 downto 25) := z(28 downto 25);
end if;

–Unidades de mil (4 bits)
if z(32 downto 29) > 4 then
z(32 downto 29) := z(32 downto 29) +3;
else z(32 downto 29) := z(32 downto 29);
end if;

–Decenas de mil (4 bits)
if z(36 downto 33) > 4 then
z(36 downto 33) := z(36 downto 33) +3;
else z(36 downto 33) := z(36 downto 33);
end if;

— Corrimiento a la izquierda.
z(36 downto 1) := z(35 downto 0);
end loop;
s_num_bcd_volt <= z(36 downto 17);
end process;

num_bcd_volt <= s_num_bcd_volt;

end BH;